In fabrication of bipolar transistors for silicon integrated circuits, a conventional "double-polysilicon" structure is formed with two layers of polysilicon, using a first polysilicon layer for base electrodes and a second polysilicon layer for an emitter electrode. Polysilicon is a preferred emitter material compared with single crystal silicon to improve forward current gain of the transistor. Thus, increased doping of the base can be used to prevent premature punchthrough when using shallow base widths required for high speed operation. In a double-polysilicon structure, the collector-base overlap area may be reduced if the extrinsic base contact is opened in an area of the base polysilicon layer which extends over a field isolation layer, rather than directly over the active device area. Thus the collector-base parasitic capacitance is reduced, and reduced spacing between a self-aligned emitter and base electrodes may be achieved.
Processes are known for fabrication of bipolar transistors having a self-aligned structure, using a first polysilicon layer for the extrinsic base contact and a second polysilicon layer for the emitter contact, for example as described in an article entitled "High Speed Polysilicon Emitter-Base Bipolar Transistor" by Hee K. Park et al., IEEE Electron Device Letters, EDL-7 No. 12 December 1986. Self-alignment of the base and the emitter allows for minimization of both the extrinsic base resistance and the collector-base junction capacitance.
In a conventional known process for fabricating a bipolar transistor for a bipolar and complementary metal oxide semiconductor (BiCMOS) integrated circuit, a typical process flow includes the following steps: a substrate is provided in the form of semiconductor wafer having an N epitaxial (epi-)layer overlying a N+ buried layer. The latter forms a buried collector. A device well region is defined in the N epi-layer and a field oxide isolation layer is formed surrounding the device well region. Then a first (base) polysilicon layer is deposited overall, extending over the device well region. The first polysilicon layer is photoengraved (PE) and etched to open a hole in first polysilicon layer, which forms an emitter opening. An intrinsic base region is formed in the device well within the emitter opening. A dielectric layer, typically silicon dioxide, is formed over first polysilicon layer, and dielectric sidewall spacers are formed on exposed sidewalls of the base polysilicon layer defining the emitter opening. A second polysilicon layer is then deposited, forming an emitter-base junction on the intrinsic base region, and the second polysilicon layer patterned to form an emitter structure isolated from the base polysilicon layer by the dielectric layer and the sidewall spacers. Contacts to the first and second polysilicon layers are then formed in a conventional manner.
The latter double-polysilicon process requires deposition of first and second polysilicon layers and the resulting structure has highly non-planar topography. In particular, the topography of the polysilicon layer forming the emitter may have a sharp discontinuity in the emitter region, requiring a very thick polysilicon layer to fill the emitter opening without leaving voids. The non-planar topography of the thick polysilicon layer complicates subsequent processing steps, including metallization and dielectric planarization, and creates problems in contact imaging, and contact etch selectivity. The depth differential of the contact to the emitter and the contact to a sinker for contacting the collector (or to a nearby CMOS well contact in a BiCMOS process) may be very large, and the contacts are in close proximity to one another. The resulting high aspect ratio contact holes are difficult to silicide, and contact etch selectivity to the underlying layers may be a problem.
A major disadvantage of this latter process is that there is a risk of damage to the emitter-base junction area of the substrate silicon during etching of the emitter opening in the first polysilicon layer, because there is no etch stop, i.e. there is little or no etch selectivity for etching polysilicon relative to the underlying silicon. Damage to the emitter-base junction region due to over-etching can have severe implications for device reliability, e.g. increased transistor noise which is detrimental to analogue applications. If the sidewall spacer oxide has incomplete conformality, variable recessing of the base during silicon over-etch, and consequent sidewall spacer width variability, can lead to variability in emitter width. The ensuing variations in emitter-base capacitance along the sidewall spacer edge and emitter polysilicon contact area cannot be avoided without exacerbating the topography related problems.
Furthermore, the process does not allow for the link region of the base to be more deeply or more heavily doped than the base implant doping, leading to higher than desirable base resistance and/or emitter-base edge leakage problems.
Thus, the latter process for a double-polysilicon self-aligned NPN bipolar transistor is complex and suffers from a number of process related problems, which lead to issues including poor manufacturability, i.e. low yield, and unsatisfactory device reliability.
As described in an article entitled "A High Speed Bipolar Technology Featuring Self-Aligned Single Poly Base And Submicrometer Emitter Contacts" by W. M. Huang et al. IEEE Electron Device Letters vol. 11, No. 9, September 1990, problems with etching double polysilicon structures may be avoided by fabricating the emitter contact with the first layer of polysilicon. The latter process is known as the "STRIPE" (self-aligned trench isolated polysilicon electrodes) process. The polysilicon layer is etched to define trenches for isolating the emitter region from the base regions. A low energy boron implant into the trench region defines a link region. Then the trench is filled with oxide and then the emitter region is N+ doped by an arsenic implant. This process reduces the possibility of etch damage of the active emitter area and avoids the highly non-planar topography of the conventional double polysilicon process. However, other process related problems remain in the PE and subsequent processing steps, including etching of the polysilicon layer to form narrow trenches (0.2 to 0.4 .mu.m) for isolation between the emitter and base regions.
Another approach to forming a single polysilicon self-aligned bipolar transistor, comprises forming a base region in the device well similarly as described above, and then forming an emitter structure by depositing a layer of polysilicon overall, patterning and etching the polysilicon to leave an emitter structure in the form of a mesa, and isolating the emitter mesa with oxide sidewall spacers, and then forming contacts to the base contact region surrounding the emitter mesa. For example, a process of this type described in U.S. Pat. No. 5,055,419 to Scovell, entitled "Method Of Manufacturing A Bipolar Transistor", issued 8 Oct. 1991. However, the latter process does not avoid the risk of damage to the underlying silicon layer in the base contact region during overetching of the polysilicon layer defining the mesa.
While other processes for formation of bipolar transistors are known, it is also desirable for bipolar CMOS integrated circuits that a process for forming a bipolar transistor should be compatible with conventional known silicon technology for CMOS processes, so that optimal performance of both bipolar and CMOS devices can be achieved without unduly adding to the overall number of process steps and process complexity.